[Back]


Talks and Poster Presentations (with Proceedings-Entry):

A. Dervic, S. S. Kohneh Poushi, H. Zimmermann:
"Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-µm CMOS for reaching PDP saturation at 650 nm";
Talk: DDECS 2021, Vienna; 04-07-2021 - 04-09-2021; in: "24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems", (2021), ISBN: 978-1-6654-3595-6; 1 - 5.



English abstract:
This paper presents a fully-integrated optical sensor
IC with SPAD, quenching/resetting circuit, and novel sensing
stage based on a tunable-threshold inverter optimized for 0.35-µm high-voltage CMOS technology. The presented quencher features a controllable excess bias voltage and an adjustable total dead time. The excess bias voltage ranges from 10 V to a maximum of 22 V. The dead time ranges from 8 ns to 50 ns, which corresponds to a saturation count rate range from 20 Mcps to 125 Mcps. The quencher is optimized for the SPAD with a capacitance of 150fF in the HV CMOS technology used. Using our recently published photon detection probability (PDP) model and fitting it to measured results up to a PDP of 68.8% at 9.9 V excess bias from our previous tapeout, a peak PDP of 90.1% (saturation PDP) at 650 nm for VEX=17.9 V is estimated and a PDP over 50% at 850 nm comes into reach for the same excess bias voltage. To the authors' best knowledge, PDP saturation has never been reached before for an integrated SPAD.

Keywords:
Avalanche photodiode (APD), CMOS technology, optical sensor, photon counting, quenching circuit, single-photon avalanche diode (SPAD).


"Official" electronic version of the publication (accessed through its Digital Object Identifier - DOI)
http://dx.doi.org/10.1109/DDECS52668.2021.9417020


Created from the Publication Database of the Vienna University of Technology.