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L. Huang, J. Wang, M. Ebrahimi, M. Daneshtalab, X. Zhang, G. Li, A. Jantsch:
"Non-blocking Testing for Network-on-Chip";
IEEE Transactions on Computers, 65 (2016), 3; S. 679 - 692.

achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical
failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network
cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approach
which could test multiple routers simultaneously at high speed without blocking or dropping packets. We first introduce a reconfigurable
router architecture allowing the cores to keep their connections with the network while the routers are under test. A deadlock-free and
highly adaptive routing algorithm is proposed to support reconfigurations for testing. In addition, a testing sequence is defined to allow
testing multiple routers to avoid dropping of packets. A procedure is proposed to control the behavior of the affected packets during the
transition of a router from the normal to the testing mode and vice versa. This approach neither interrupts the execution of applications
nor has a significant impact on the execution time. Experiments with the PARSEC benchmarks on an 8x8 NoC-based chip
multiprocessors show only 3% execution time increase with four routers simultaneously under test

nfigurable Router Architecture, Built-In Self-Test, On-chip interconnect, Single-chip multiprocessors

http://dx.doi.org/10.1109/TC.2015.2489216