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Talks and Poster Presentations (with Proceedings-Entry):

B. Goll, H. Zimmermann:
"A Low-Power 2-GSample/s Comparator in 120 nm CMOS Technology";
Talk: European Solid-State Circuits Conference, Grenoble, France; 09-12-2005 - 09-16-2005; in: "Proceedings of ESSCIRC 2005", (2005), ISBN: 0-7803-9205-1; 507 - 510.



English abstract:
This paper presents a comparator in 120nm digital CMOS technology with a supply voltage of 1.5V. In contrast to common comparator structures a delayed reset signal is used to enhance the output voltage difference with the help of charge injection. Furthermore the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution. For characterization several BER (Bit-Error-Rate) measurements on the comparator have been made. For a BER of 10-9 the comparator is able to detect an input voltage difference of 9.5mV at a clock frequency of 1.5GHz and 16mV at 2.0GHz. The maximum power consumption of the comparator with two following additional transfer stages is 360μW at 2.0GHz.


Online library catalogue of the TU Vienna:
http://aleph.ub.tuwien.ac.at/F?base=tuw01&func=find-c&ccl_term=AC05935493


Created from the Publication Database of the Vienna University of Technology.